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A3979 Microstepping DMOS Driver with Translator
Features and Benefits
2.5 A, 35 V output rating Low RDS(On) outputs: 0.28 source, 0.22 sink, typical Automatic current decay mode detection/selection 3.0 to 5.5 V logic supply voltage range Slow, Fast or Mixed current decay modes Home output Synchronous rectification for low power dissipation Internal UVLO and thermal shutdown circuitry Crossover-current protection
Description
The A3979 is a complete microstepping motor driver with built-in translator, designed as a pin-compatible replacement for the successful A3977, with enhanced microstepping (1/16 step) precision. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step modes, with an output drive capacity of up to 35 V and 2.5 A. The A3979 includes a fixed off-time current regulator that has the ability to operate in Slow, Fast, or Mixed decay modes. This current-decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. The translator is the key to the easy implementation of the A3979. It allows the simple input of one pulse on the STEP pin to drive the motor one microstep, which can be either a full step, half, quarter, or sixteenth, depending on the setting of the MS1 and MS2 logic inputs. There are no phase-sequence tables, high-frequency control lines, or complex interfaces to program. The A3979 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. Internal synchronous-rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, UVLO (undervoltage lockout), and crossover-current protection. Special power-on sequencing is not required.
Package: 28 lead TSSOP (suffix LP) with exposed thermal pad
Not to scale
The A3979 is supplied in a low-profile (height 1.20 mm), 28-pin TSSOP with exposed thermal pad. The package is lead (Pb) free, with 100% matte tin leadframe plating.
Pin-out Diagram
SENSE1 1 HOME 2 DIR 3 OUT1A 4 PFD 5 RC1 6 AGND 7 REF 8 RC2 9 VDD 10 OUT2A 11 MS2 12 MS1 13 SENSE2 14 /8
PWM Timer Charge Pump
28 VBB1 27 SLEEP 26 ENABLE 25 OUT1B 24 CP2 Translator and Control Logic 23 CP1 22 VCP 21 PGND Reg 20 VREG 19 STEP 18 OUT2B 17 RESET 16 SR 15 VBB2
AGND and PGND must be connected together externally
26184.23D
A3979
DMOS Microstepping Driver with Translator
Selection Guide
Part Number A3979SLP-T A3979SLPTR-T Packing 50 pieces per tube 4000 pieces per reel
Absolute Maximum Ratings
Load Supply Voltage Output Current Logic Supply Voltage Logic Input Voltage Range Sense Voltage Reference Voltage Operating Ambient Temperature Junction Temperature Storage Temperature VBB IOUT VDD VIN VSENSE VREF TA TJ(max) Tstg Range S tW > 30 ns tW < 30 ns Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150C. 35 2.5 7.0 -0.3 to VDD + 0.3 -1 to VDD + 1 0.5 VDD -20 to 85 150 -55 to 150 V A V V V V V C C C
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3979
DMOS Microstepping Driver with Translator
Functional Block Diagram
0.22 F
0.22 F
VREG Logic Supply VDD UVLO and Fault Regulator Bandgap 2V
CP2
CP1
Charge Pump VCP
Reference Supply REF DAC DMOS Full Bridge
0.22 F Load Supply VBB1 >47 F 4 OUT1A OUT1B PWM Timer: PWM Latch Blanking Mixed Decay Gate Drive 4 Control Logic DMOS Full Bridge VBB2
RC1 STEP RT1 CT1 DIR RESET MS1 MS2 HOME SLEEP SR ENABLE VPFD PFD 0.1 F RC2 PWM Timer: PWM Latch Blanking Mixed Decay OUT2A OUT2B Translator
SENSE1 RS1 CS1
SENSE2
RT2
CT2
DAC
RS2
CS2
Exposed Thermal Pad AGND PGND
(Required)
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3979
DMOS Microstepping Driver with Translator
ELECTRICAL CHARACTERISTICS at TA = 25C, VBB = 35 V, VDD = 3.0 to 5.5 V (unless otherwise noted)
Characteristics Output Drivers Load Supply Voltage Range Output Leakage Current2 Output On Resistance Body Diode Forward Voltage Symbol Test Conditions Operating During Sleep mode VOUT = VBB VOUT = 0 V Source driver, IOUT = -2.5 A Sink driver, IOUT = 2.5 A Source diode, IF = -2.5 A Sink diode, IF = 2.5 A fPWM < 50 kHz Operating, outputs disabled Sleep mode Operating fPWM < 50 kHz Outputs off Sleep mode Min. 8 0 - - - - - - - - - 3.0 - - - 0.7x VDD - VIN = 0.7 x VDD VIN = 0.3 x VDD Operating -20 -20 0 - 0.7x VDD - - - VREF = 2 V, Phase Current = 38.27% VREF = 2 V, Phase Current = 70.71% VREF = 2 V, Phase Current = 100.00% RT = 56 k, CT = 680 pF RT = 56 k, CT = 680 pF Synchronous rectification enabled - - - 1 700 30 100 Typ.1 - - <1.0 <1.0 0.28 0.22 - - - - - 5.0 - - - - - <1.0 <1.0 - 0 - - 0.6 xVDD 0.21xVDD - - - - 950 38 475 Max. 35 35 20 -20 0.335 0.265 1.4 1.4 8.0 6.0 20 5.5 12 10 20 - 0.3 xVDD 20 20 VDD 3 - 0.3x VDD - - 10 5.0 5.0 - 1200 46 800 Units V V A A V V mA mA A V mA mA A V V A A V A V V V V % % % s ns s ns
VBB IDSS RDS(On) VF IBB
Motor Supply Current Control Logic Logic Supply Voltage Range Logic Supply Current
VDD IDD VIN(1) VIN(0) IIN(1) IIN(0) VREF IREF
Logic Input Voltage Logic Input Current2 Reference Input Voltage Range Reference Input Current HOME Output Voltage Mixed Decay Mode Trip Point
VHOME(1) IHOME(1) = -200 A VHOME(0) IHOME(0) = 200 A VPFDH VPFDL
EG
Gain (Gm) Error3 STEP Pulse Width Blank Time Fixed Off-Time Crossover Dead Time
tW tBLANK tOFF tDT
Continued on the next page...
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3979
DMOS Microstepping Driver with Translator
ELECTRICAL CHARACTERISTICS, continued at TA = 25C, VBB = 35 V, VDD = 3.0 to 5.5 V (unless otherwise noted)
Characteristics Thermal Shutdown Temperature Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Symbol Test Conditions TJSD TJSDHYS VUVLO Increasing VDD VUVLOHYS Min. - - 2.45 0.05 Typ.1 165 15 2.7 0.10 Max. - - 2.95 - Units C C V V
1Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 2Negative current is defined as coming out of (sourcing from) the specified device pin. 3E = ( [ V G REF / 8] - VSENSE ) / ( VREF / 8 ).
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Two-layer PCB with 3.8 in.2 of copper area on each side connected with thermal vias and to device exposed pad High-K PCB (multilayer with significant copper areas, based on JEDEC standard) Value 32 28 Units C/W C/W
Package Thermal Resistance
RJA
*Additional thermal information available on Allegro Web site.
Maximum Power Dissipation, PD(max)
5.0 4.5 4.0
H (R ighJ A
Power Dissipation, PD (W)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
2La ye
rP ) (R CB w ith J A= 3 32 .8 in 2 C co /W pp er ) p
K = PCB 28 C /W
er
sid
e
20
40
60
80 100 120 Temperature (C)
140
160
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3979
DMOS Microstepping Driver with Translator
Timing Requirements (TA = +25C, VDD = 5 V, Logic Levels are VDD and Ground)
STEP
50%
C A B
D
MS1/MS2/ DIR/RESET
E
SLEEP
Dwg. WP-042
A. Minimum Command Active Time Before Step Pulse (Data Set-Up Time) ..... 200 ns B. Minimum Command Active Time After Step Pulse (Data Hold Time) ............ 200 ns C. Minimum STEP Pulse Width ...................... 1.0 s D. Minimum STEP Low Time ......................... 1.0 s E. Maximum Wake-Up Time ......................... 1.0 ms
Figure 1. Logic Interface Timing Diagram
Table 1. Microstep Resolution Truth Table
MS1 L H L H MS2 L L H H Microstep Resolution Full Step Half Step Quarter Step Sixteenth Step Excitation Mode 2 Phase 1-2 Phase W1-2 Phase 4W1-2 Phase
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3979
DMOS Microstepping Driver with Translator
Functional Description
Device Operation. The A3979 is a complete microstepping motor driver with a built-in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step modes. The currents in each of the two output full-bridges (all of the N-channel MOSFETs) are regulated with fixed off-time PMW (pulse width modulated) control circuitry. At each step, the current for each full-bridge is set by the value of its external current-sense resistor (RS1 or RS2), a reference voltage (VREF), and the output voltage of its DAC (which in turn is controlled by the output of the translator). At power-on or reset, the translator sets the DACs and the phase current polarity to the initial Home state (shown in figures 2 through 5), and the current regulator to Mixed decay mode for both phases. When a step command signal occurs on the STEP input, the translator automatically sequences the DACs to the next level and current polarity. (See table 2 for the current-level sequence.) The microstep resolution is set by the combined effect of inputs MS1 and MS2, as shown in table 1. While stepping is occurring, if the next output level of the DACs is lower than the immediately preceeding output level, then the decay mode (Fast, Slow, or Mixed) for the active full bridge is set by the PFD input. If the next DAC output level is higher than or equal to the preceeding level, then the decay mode for that full bridge will be Slow decay. This automatic current-decay selection improves microstepping performance by reducing the distortion of the current waveform due to back EMF of the motor.
Step Input (STEP). A low-to-high transition on the
STEP input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the combined state of inputs MS1 and MS2 (see table 1).
Microstep Select (MS1 and MS2). The input on terminals MS1 and MS2 selects the microstepping format, as shown in table 1. Any changes made to these inputs do not take effect until the next rising edge of a step command signal on the STEP input. Direction Input (DIR). The state of the DIR input determines the direction of rotation of the motor. Any changes made to this input does not take effect until the next rising edge of a step command signal on the STEP input.
Internal PWM Current Control. Each full bridge is
controlled by a fixed-off-time PWM current-control circuit that limits the load current to a desired value, ITRIP . Initially, a diagonal pair of source and sink MOS outputs are enabled and current flows through the motor winding and the current sense resistor, RSx. When the voltage across RSx equals the DAC output voltage, the current-sense comparator resets the PWM latch. The latch then turns off either the source MOSFETs (when in Slow decay mode) or the sink and source MOSFETs (when in Fast or Mixed decay mode). The maximum value of current limiting is set by the selection of RS and the voltage at the VREF input with a transconductance function approximated by:
ITRIPmax = VREF/8RS
The DAC output reduces the VREF output to the current-sense comparator in precise steps (see table 2 for
RESET Input ( ). The R input (active RESET ESET
low) sets the translator to a predefined Home state (shown in figures 2 through 5), and turns off all of the DMOS outputs. The HOME output goes low and all STEP inputs are ignored until the R input is set to high. ESET
% ITRIPmax at each step). ITRIP = (% ITRIPmax/100) ITRIPmax
It is critical that the maximum rating (0.5 V) on either the SENSE1 and SENSE2 pins is not exceeded. For full stepping, VREF can be applied up to the maximum rating of VDD because the peak sense value is 0.707 x VREF / 8. In all other modes, VREF should not exceed 4 V.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
Home Output (HOME). The HOME output is a logic
output indicator of the initial state of the translator. At power-on, the translator is reset to the Home state (shown in figures 2 through 5).
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A3979
DMOS Microstepping Driver with Translator
Fixed Off-Time. The internal PWM current-control circuitry uses a one-shot timer to control the duration of time that the MOSFETs remain off. The one shot off-time, tOFF, is determined by the selection of external resistors, RTx , and capacitors, CTx , connected from each RCx timing terminal to ground. The off-time, over a range of values of CT = 470 pF to 1500 pF and RT = 12 k to 100 k is approximated by: tOFF = RTCT
age on VCP, the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the undervoltage lockout (UVLO) circuit disables the drivers and resets the translator to the Home state.
RC Blanking. In addition to the fixed off-time of the
PWM control circuit, the CTx component sets the comparator blanking time. This function blanks the output of the current-sense comparators when the outputs are switched by the internal current-control circuitry. The comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, or to switching transients related to the capacitance of the load. The blank time tBLANK can be approximated by:
Sleep Mode ( ). This active-low control input SLEEP is used to minimize power consumption when the motor is not in use. It disables much of the internal circuitry including the output DMOS FETs, current regulator, and charge pump. Setting this to a logic high allows normal operation, as well as start-up (at which time the A3979 drives the motor to the Home microstep position). When bringing the device out of Sleep mode, in order to allow the charge pump (gate drive) to stabilize, provide a delay of 1 ms before issuing a step command signal on the STEP input. Percent Fast Decay Input (PFD). When a STEP input signal commands a lower output current than the
previous step, it switches the output current decay to either Slow, Fast, or Mixed decay mode, depending on the voltage level at the PFD input. If the voltage at the PFD input is greater than 0.6 x VDD , then Slow decay mode is selected. If the voltage on the PFD input is less than 0.21 x VDD , then Fast decay mode is selected. Mixed decay mode is selected when VPFD is between these two levels, as described in the next section. This terminal should be decoupled with a 0.1 F capacitor. Mixed Decay Operation. If the voltage on the PFD input is between 0.6 x VDD and 0.21 x VDD , the bridge operates in Mixed decay mode, as determined by the step sequence (shown in figures 2 through 5). As the trip point is reached, the device goes into Fast decay mode until the voltage on the RCx terminal decays to the same level as voltage applied to the PFD terminal. The time that the device operates in fast decay is approximated by:
tBLANK = 1400CT Charge Pump (CP1 and CP2). The charge pump is
used to generate a gate supply greater than that of VBB for driving the source-side DMOS gates. A 0.22 F ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. In addition, a 0.22 F ceramic capacitor is required between VCP and VBB, to act as a reservoir for operating the high-side DMOS gates. operate the sink-side DMOS outputs. The VREG pin must be decoupled with a 0.22 F capacitor to ground. VREG is internally monitored, and in the case of a fault condition, the DMOS outputs of the device are disabled.
VREG (VREG). This internally-generated voltage is used to
Enable Input ( ). This active-low input ENABLE
enables all of the DMOS outputs. When set to a logic high, the outputs are disabled. The inputs to the translator (STEP, DIR, MS1, and MS2), all remain active, independent of the ENABL E input state.
tFD = RTCTln (0.6VDD/VPFD)
After this Fast decay portion, the device switches to Slow decay mode for the remainder of the fixed off-time period.
Shutdown. During normal operation, in the event of a
fault, such as overtemperature (excess TJ) or an undervolt-
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3979
DMOS Microstepping Driver with Translator
Synchronous Rectification. When a PWM offcycle is triggered by an internal fixed-off-time cycle, load current recirculates according to the decay mode selected by the control logic. The A3979 synchronous rectification feature turns on the appropriate MOSFETs during the decay of the current, and effectively shorts out the body diodes with the low RDS(On) driver. This reduces power dissipation significantly and eliminates the need for external Schottky diodes for most applications. The synchronous rectification can be set to either Active mode or Disabled mode:
* Active Mode. When the SR input is logic low, Active mode is enabled and synchronous rectification can occur. This mode prevents reversal of the load current by turning off synchronous rectification when a zero current level is detected. This prevents the motor winding from conducting in the reverse direction. * Disabled Mode. When the SR input is logic high, synchronous rectification is disabled. This mode is typically used when external diodes are required to transfer power dissipation from the A3979 package to the external diodes.
Applications Information
Layout. The printed circuit board on which the device is
mounted should have a heavy ground plane. For optimum electrical and thermal performance, the A3979 should be soldered directly onto the board. The load supply terminals, VBBx, should be decoupled with an electrolytic capacitor (>47 F is recommended), placed as close to the device as possible. To avoid problems due to capacitive coupling of the high dv / dt switching transients, route the bridge-output traces away from the sensitive logic-input traces. Always drive the logic inputs with a low source impedance to increase noise immunity.
Current Sensing. To minimize inaccuracies caused by
ground-trace IR drops in sensing the output current level, the current-sense resistors, RSx, should have an independent ground return to the star ground of the device. This path should be as short as possible. For low-value sense resistors, the IR drops in the printed circuit board sense resistor traces can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in RSx due to their contact resistance. Allegro MicroSystems recommends a value of RS given by
Grounding. The AGND (analog ground) terminal and the
PGND (power ground) terminal must be connected together externally. All ground lines should be connected together and be as short as possible. A star ground system, centered under the device, is an optimum design. The copper ground plane located under the exposed thermal pad is typically used as the star ground.
RS = 0.5/ITRIPmax Thermal Protection. This internal circuitry turns off
all drivers when the junction temperature reaches 165C, typical. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15C.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3979
DMOS Microstepping Driver with Translator
STEP Input HOME Output
100.00 70.71
STEP Input HOME Output
100.00 70.71
Slow
Slow Mixed
Slow Mixed
Home Microstep Position
Home Microstep Position
Home Microstep Position
-70.71 -100.00 100.00 70.71
-70.71 -100.00 100.00 70.71
Slow Slow Mixed Mixed
Slow Mixed
Slow
Phase 2 IOUT2A Direction = H (%)
0.00
Slow
-70.71
Phase 2 IOUT2B Direction = H (%)
0.00
-70.71 -100.00
-100.00
Figure 2. Decay Mode for Full-Step Increments
STEP Input HOME Output
100.00 92.39 70.71 38.27
Figure 3. Decay Modes for Half-Step Increments
-38.27 -70.71 -92.39 -100.00 100.00 92.39 70.71 38.27
Slow Mixed Slow Mixed Slow Mixed
Phase 2 IOUT2B Direction = H (%)
0.00
-38.27 -70.71 -92.39 -100.00
Figure 4. Decay Modes for Quarter-Step Increments
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
Home Microstep Position
Phase 1 IOUT1A Direction = H (%)
Slow
0.00
Mixed
Slow
Mixed
Slow
Home Microstep Position
Phase 1 IOUT1A Direction = H (%)
Slow
0.00
Phase 1 IOUT1A Direction = H (%)
Mixed
0.00
10
A3979
DMOS Microstepping Driver with Translator
STEP Input HOME Output
100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51
Phase 1 IOUT1A Direction = H (%)
9.8
Slow
0.00 -9.8 -19.51 -29.03 -38.27 -47.14 -55.56 -63.44 -70.71 -77.30 -83.15 -88.19 -95.69 -100.00 100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51
Mixed
Slow
Mixed
Phase 2 IOUT2B Direction = H (%)
9.8 0.00 -9.8 -19.51 -29.03 -38.27 -47.14 -55.56 -63.44 -70.71 -77.30 -83.15 -88.19 -95.69 -100.00
Slow Mixed Slow Mixed Slow
Figure 5. Decay Modes for Sixteenth-Step Increments
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
Home Microstep Position
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A3979
DMOS Microstepping Driver with Translator
Table 2. Step Sequencing Settings
Home microstep position at Step Angle 45; DIR = H; 360 = 4 full steps
Full Step #
Half Step # 1
1/4 Step # 1
1/16 Step # 1 2 3 4
Phase 1 Current
[% ItripMax]
Phase 2 Current
[% ItripMax]
(%) 100.00 99.52 98.08 95.69 92.39 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.80 0.00 -9.80 -19.51 -29.03 -38.27 -47.14 -55.56 -63.44 -70.71 -77.30 -83.15 -88.19 -92.39 -95.69 -98.08 -99.52
(%) 0.00 9.80 19.51 29.03 38.27 47.14 55.56 63.44 70.71 77.30 83.15 88.19 92.39 95.69 98.08 99.52 100.00 99.52 98.08 95.69 92.39 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.80
Step Angle () 0.0 5.6 11.3 16.9 22.5 28.1 33.8 39.4 45.0 50.6 56.3 61.9 67.5 73.1 78.8 84.4 90.0 95.6 101.3 106.9 112.5 118.1 123.8 129.4 135.0 140.6 146.3 151.9 157.5 163.1 168.8 174.4
Full Step #
Half Step # 5
1/4 Step # 9
1/16 Step # 33 34 35 36
Phase 1 Current
[% ItripMax]
Phase 2 Current
[% ItripMax]
Step Angle
()
(%)
-100.00 -99.52 -98.08 -95.69 -92.39 -88.19 -83.15 -77.30 -70.71 -63.44 -55.56 -47.14 -38.27 -29.03 -19.51 -9.80 0.00 9.80 19.51 29.03 38.27 47.14 55.56 63.44 70.71 77.30 83.15 88.19 92.39 95.69 98.08 99.52
(%) 0.00 -9.80 -19.51 -29.03 -38.27 -47.14 -55.56 -63.44 -70.71 -77.30 -83.15 -88.19 -92.39 -95.69 -98.08 -99.52 -100.00 -99.52 -98.08 -95.69 -92.39 -88.19 -83.15 -77.30 -70.71 -63.44 -55.56 -47.14 -38.27 -29.03 -19.51 -9.80
180.0 185.6 191.3 196.9 202.5 208.1 213.8 219.4 225.0 230.6 236.3 241.9 247.5 253.1 258.8 264.4 270.0 275.6 281.3 286.9 292.5 298.1 303.8 309.4 315.0 320.6 326.3 331.9 337.5 343.1 348.8 354.4
2
5 6 7 8
10
37 38 39 40
1
2
3
9 10 11 12
3
6
11
41 42 43 44
4
13 14 15 16
12
45 46 47 48
3
5
17 18 19 20
7
13
49 50 51 52
6
21 22 23 24
14
53 54 55 56
2
4
7
25 26 27 28
4
8
15
57 58 59 60
8
29 30 31 32
16
61 62 63 64
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3979
DMOS Microstepping Driver with Translator
Terminal List Table Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name SENSE1 HOME DIR OUT1A PFD RC1 AGND REF RC2 VDD OUT2A MS2 MS1 SENSE2 VBB2 SR RESET OUT2B STEP VREG PGND VCP CP1 CP2 1OUT1B ENABLE SLEEP VBB1 Logic Output Logic input Output A for Bridge 1 Mixed decay setting Analog input for fixed off-time for Bridge 1 Analog Ground Current trip reference voltage input Analog input for fixed off-time for Bridge 2 Logic supply Output A for Bridge 2 Logic input Logic input Sense resistor for Bridge 2 Load supply for Bridge 2 Logic input Logic input Output B for Bridge 2 Logic input Regulator decoupling Power Ground Reservoir capacitor Charge pump capacitor 1 Charge pump capacitor 2 Output B for Bridge 1 Logic input Logic input Load supply for Bridge 1 Description Sense resistor for Bridge 1
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3979
DMOS Microstepping Driver with Translator
LP Package, 28-pin TSSOP
9.70 0.10 28 4 4 +0.05 0.15 -0.06 1.65 28
0.45
0.65
B 3.00 A 4.40 0.10 6.40 0.20 0.60 0.15 (1.00) 3.00 6.10
1
2 5.00 0.25 SEATING PLANE 0.65 1.20 MAX 0.10 MAX For reference only (reference JEDEC MO-153 AET) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) C SEATING PLANE GAUGE PLANE 12 5.00 C PCB Layout Reference View
28X 0.10 C +0.05 0.25 -0.06
Copyright (c)2005-2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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